CADENCE DESIGN SYSTEMS INC CDNS
December 13, 2023 - 6:20pm EST by
madmax989
2023 2024
Price: 277.00 EPS 0 0
Shares Out. (in M): 281 P/E 0 0
Market Cap (in $M): 77,578 P/FCF 0 0
Net Debt (in $M): -313 EBIT 0 0
TEV (in $M): 77,265 TEV/EBIT 0 0

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  • please write up more wildly expensive stupid stocks that you're not involved with
  • Valuation doesn't matter in this mkt anyway
  • Valuation is irrelevant just buy momentum tech
  • Outrageously overvalued
 

Description

Overview

Note that a discussion of Cadence Design Systems, Inc. (ticker: CDNS) requires a fair bit of technical jargon, so we have included a glossary as an Appendix with all acronyms and technical terms we use throughout the document. 

Cadence is one of the most important companies that no one has ever heard of. The company provides software, hardware, services, and reusable IC design blocks for semiconductor customers to design, configure, analyze, and verify ICs, and for systems companies to design, simulate, and verify electro-thermal and physical functionality of their ICs, PCBs, and systems products. Through these products and services, Cadence helps customers to optimize performance, minimize power consumption, shorten time to market, improve engineering productivity and reduce design, development, and manufacturing costs.

Cadence’s core competency is in computational software (computer science plus math), where they think they are the best in the world. They offer mission critical products and services – the software and hardware needed to design and test chips and electronic systems – that are low-cost relative to the value they provide.

Cadence boasts a strong competitive advantage centered in predictable and largely contractually recurring revenues, a stable oligopoly industry structure with scale, outstanding management, a pristine balance sheet, excellent financial returns, and strong growth prospects. Cadence is a broad-based play on the R&D expenditures of semiconductor design and manufacturing companies. It trades at a reasonable price relative to its prospects and quality and affords investors an attractive risk-adjusted return profile.

Cadence is a great way to play secular growth in AI and chips more broadly.

Note that Cadence has a December fiscal yearend. All references to LTM are to the 12-month period ending September 2023, unless otherwise noted. 

Note that we deduct stock-based compensation as a regular expense in all our profit calculations. Other than including stock-based compensation, we accept all of management’s other income statement adjustments as appropriate. 

The Business

Cadence is largely a “picks and shovels” services provider to designers of all things electronic. The company creates software and hardware to help customers develop electronic products, including ICs, SoCs, devices, and systems. In essence, they are helping customers create a blueprint for a chip, with its billions of microscopic transistors. Cadence then tests and verifies the functionality of those designs, both at the chip and system level. 

Cadence addresses customer needs for better performance, lower power consumption, shorter time to bring their products to market, better engineering productivity, and lower costs (design, development, and manufacturing). Cadence sells software, hardware, its own reusable IP chip design blocks, and related services. 

Before getting into the business, it’s worth taking a moment to go through the process of making a chip. Chip designers (i.e., Nvidia, Tesla, or Apple) will gather a group of engineers to begin working on a new design (a “design start”). They’ll incorporate some existing IP for processes that do not need to be reinvented (like the ability to charge the battery through a USB). They will license this IP from third parties (i.e., Arm, Synopsys, or Cadence) who have developed and proven out the technology. They will use EDA software (from Cadence or Synopsys) to design the chip and optimize for the characteristics it seeks (PPA, yield, heat, etc.). They will simulate the chip both on software and on hardware (from Cadence or Synopsys) to verify functionality at many stages along the way. They’ll partner with foundries (i.e., TSMC or Samsung) to ensure the manufacturing process will work as planned. They’ll then “tape out” the design for a first silicon manufacturing run, including creating a photomask (kind of like a stencil for the chip) and give that to the foundry. Then the foundry produces the chips in volume to be incorporated into electronic systems (which are typically built by system integrators, like Flex or Hon Hai/Foxconn). Cadence and its closest competitor, Synopsys, can both offer what’s called “full flow,” which means a customer can complete the entire chip design process using Cadence or Synopsys. 

Cadence has two main customer groups: chip designers and system designers: 

  • Chip designers (~55% of revenue): Chip designers create computer chips. Examples include companies like Nvidia, Broadcom, Arm, and Analog Devices (some of whom also design systems). These companies develop ICs and related subcategories like processors, SoCs, AI, memory, analog, digital, and other types of chips. Chip customers use Cadence’s tools to design, configure, analyze, and verify the functionality of their ICs. All the top 20 semiconductor companies use Cadence’s digital software, and half of them use Cadence’s Cerebrus AI solution. 

  • System designers (~45% of revenue): System designers create mobile phones, laptop and desktop computers, gaming systems, automobiles and the ADAS needed for autonomous driving, servers, cloud data center infrastructure, AI systems, aerospace and defense, medical equipment, and networking products, among other things. Examples would be firms like Apple, Meta, Dell, and Tesla (some of whom also design chips). These companies develop or purchase the sub-components for their products, including PCBs, ICs, and software. System designers use Cadence’s tools to design, simulate, and verify the electro-thermal and physical functionality of their ICs, PCBs, and systems products. This includes both the silicon (internally developed chips) and non-silicon (the holistic systems themselves) revenues coming from the systems companies. The non-silicon systems area is smaller, newer, higher margin, and grows faster for Cadence than its other business lines.

Historically, Cadence played in the EDA industry. Over the last decade or so, however, Cadence has broadened its reach beyond EDA and now reports revenue in five buckets (we have included CDNS’s description of these segments in an Appendix): 

  • Custom IC Design and Simulation (21% of LTM revenue): customers license Cadence’s software to create schematic and physical representations of circuits down to the transistor level for analog, mixed signal, custom digital, memory, and RF designs. They then use tools optimized for each type of design to verify functionality at various points in the design process, including design capture, simulation, IC layout, and prep for manufacturing. Cadence has verification tools for the chip, package, and PCB. Among some of their more advanced solutions, Cadence offers products for three-dimensional transistors (FinFETs, GAA) and multi-patterning. 

  • Digital Design and Signoff (27% of LTM revenue): customers license Cadence’s software to create logical representations of a digital circuit or an IC. They then use Cadence tools to verify the design is correct prior to implementation. Once verified, customers use other Cadence tools to implement the design representation or convert it to a format ready for silicon manufacturing. 

  • Functional Verification (28% of LTM revenue): customers use these products to verify that their designs for circuitry or software are consistent with their functional specification. Cadence’s EDA tools simulate the design environment so that customers can see the tradeoffs in different factors like power and performance. They can then iterate until they have optimized the design for whatever constraints they have to manage. Recently, EDA companies have been using AI to help in this design optimization, which is becoming more important as the number of design parameters proliferates. Verification takes place throughout the design process, with a goal to identify as many potential functional problems as possible before manufacturing. Errors in the completed project can be extremely costly both in terms of dollars and time, so customers will go to great lengths to surface them early. Cadence offers different verification tools for each stage of the design process, and in total verification can take up to 70% of the total time to design a chip (per Morgan Stanley). Most of Cadence’s hardware sales are in this segment.

  • IP (11% of LTM revenue): customers license Cadence’s internally developed and verified chip design blocks to integrate into their own ICs on a non-exclusive basis. By using Cadence’s pre-designed functional blocks, customers can accelerate their own product development processes and reduce the risk of errors. Cadence’s most popular IP include configurable DSPs, vertically targeted subsystems for AI, audio/voice, baseband and vision/imaging, controllers and physical interfaces for standard protocols, analog IP, high speed SerDes, PCI, and USB. They also offer verification IP. 

  • SD&A (13% of LTM revenue): customers use Cadence’s offerings to develop systems (rather than just chips), including PCBs and advanced IC packages, and to analyze properties for these systems, including electromagnetic, electro-thermal, CFD, and other multiphysics effects (aerodynamics, hydrodynamics, propulsion, turbomachinery, heat transfer, combustion). The speed and proximity of signals on silicon (through packages on to boards, and through connectors and cables) exposes these electrical communications to various kinds of interference, like heat and electromagnetic radiation. Cadence’s tools can analyze and simulate these products to ensure they work as designed. 

Cadence typically licenses their products to customers for finite terms, generally for three years plus add-ons purchased intermittently. As the add-ons attach with a co-terminus basis, the weighted average contract term is around 2.5 years. EDA is sold almost entirely on a subscription basis, typically per seat. 

Cadence also sells or leases emulation and prototyping hardware. Emulation hardware is used to emulate a chip before it’s manufactured, giving customers the ability to run software on top of it, run tests, boot Windows or Android or run an AI stack, all before the chip goes to manufacturing. Emulation is an important and required process in chip design. Hardware sales, like software sales, tend to be tied to the number and size of customer designs.

Cadence has about 10k employees, with around 80% being engineers either in R&D or in the field. The company is based in San Jose, CA.

Cadence competes primarily with Synopsys in EDA. Siemens, which purchased EDA competitor Mentor Graphics in 2017 for $4.5 billion, is also a meaningful #3. Ansys is a more distant #4 in EDA, but is a major competitor in SD&A. Several upstart Chinese competitors are also trying to get a foothold in EDA, though with limited success so far.

Management

CEO Anirudh Devgan has been with Cadence since 2012, having come up through the R&D groups before being made President in late 2017 and CEO in December 2021. He joined Cadence from a competitor called Magma Design, where he was general manager of the Custom Business Design Unit, when it was acquired by Synopsys. Devgan received his B.Tech in electrical engineering from the Indian Institute of Technology in Delhi, and an M.S. and Ph.D. in electrical and computer engineering from Carnegie Mellon. Given the prevalence of engineers in the firm, it is important that the CEO has a strong background in engineering and computer science.

Devgan is not just well-educated and highly intelligent. He is methodical, thoughtful, purposeful, concise, and grounded. He is only 54 years old, and only a couple of years into the role, so we expect him to be there a long time. The CFO John Wall credits him with dramatically improving Cadence’s digital EDA capabilities to compete with Synopsys prior to his becoming CEO. This required making a product that wasn’t just good, but much better, to induce customers to switch. Devgan overhauled the product entirely, and his playbook became the foundation for Cadence’s more recent entry into SD&A. 

Devgan took over the helm from Lip-Bu Tan, who ran Cadence from 2009 to late 2021. Tan did wonderful things for Cadence. Prior to Tan taking the reins, Cadence was really struggling. The company massively underpriced the product, had unfocused management, and engaged in self-destructive industry practices including poor salesforce incentives. The onset of the great financial crisis pushed Cadence close to the brink. In 2009 and the ensuing few years, Tan came in and overhauled management, made a prescient move into a subscription pricing model founded on value-based pricing, greenlit Devgan to invest aggressively into digital EDA, conducted intelligent M&A, and later promoted Wall to CFO. He turned the company around in a major way and set Cadence on a great path. 

Wall himself deserves mentioning too. He started with the company 26 years ago and became CFO in 2017 (which was around when he started working closely with then President Devgan). At that time, growth was decelerating, and incremental margins were too low. He set the bar for margins much higher and took a close look at R&D, where most of the company’s investment is and was made. He found that roughly two-thirds of engineering time was spent on maintaining existing products while only one-third was on new products. Using internal data, he determined that the company was rushing products out the door before they were ready and then spending too much time working on bugs and fixes. His suggestion was to slow down the pace of introductions and focus energy on building new products right before pushing them out to customers. He also made engineers compete for investment dollars. Per Wall in August 2023, “They're dangerous now. They come looking for investment dollars, and they're showing us the press release, what the press release will look like. If you give me the dollars to do this. But I think they're much better at focusing. Like -- thinking like an investor, thinking like an owner and choosing projects or allocating the investment dollars to projects that they think will generate a return for investment. … I do a general allocation, and then I tend to tax all of the R&D groups. If you're doing the same thing as you did last year, I expect you to do it more efficiently. So we take 2% or 3% off of them, create an investment pool for Anirudh to allocate to new projects. And then we just encourage the teams to compete for those and try to think like owners in the efforts that they take on.” Through these efforts, Wall has flipped the old math, with most engineering time now spent on new products. He has given other examples too, like how he improved value selling among the sales teams. He also considers engineers to be the scarce resource, so he focuses a great deal on productivity to ensure the company is using its engineers’ time wisely (see Cadence vs. Synopsys section below). In general, Wall has been a data-driven leader who understands incentives, and he’s overseen a dramatic improvement in margins. The results speak for themselves (see Financial Results section below). 

He’s also been thoughtful in how he goes about allocating capital to share buybacks. He targets using 50% of free cash flow to offset dilution from stock comp and to reduce the share count. Here is Wall on how he thinks about it: “When I'm looking at things like our buyback policy for repurchasing shares, I'm always looking at the net present value of future cash flows. So we do this model, it kind of looks out a couple of decades to see what net present value, future cash flows look like. And just as an exercise, I wanted to look at what does it look like if we didn't have to chase Moore's Law. If Moore's Law slows down and a growth company turns it -- morphs into a value company over time. Well, then you take your 35% that you're spending in R&D would probably decline to something like more normal, like a 5% over time. But when you do that, it's quite interesting. Multiples come down, but the cash flow generation and the profit generation more than makes up for it and the near term, the time that you're able to collect that cash, you end up with pretty similar valuations, whether Moore's Law continues on indefinitely or whether Moore's Law slows down over the next 20 years.” 

Turning to the current strategy (introduced in 2019), management pursues what it calls “Intelligent System Design,” which centers on the merger of traditional EDA with system level design and AI: 

The main objective of the design excellence approach is to enable design teams to manage increasing complexity and verification throughput for analog, digital, and mixed signal chips without commensurately increasing the team size or extending the project schedule, while also reducing technical risks. This is the core EDA and IP businesses. 

From there they are growing into two new areas. The system innovation strategic area captures Cadence’s expansion into total system capabilities, including system design, simulation (including electromagnetic, electro-thermal, and other multiphysics analysis needed to optimize total system performance), as well as advanced packaging. Pervasive intelligence is required at every step of the design, grounded in computational engineering (Cadence’s core competency). They must optimize systems, hardware, and software simultaneously and in coherent fashion. This strategic area captures the ability to provide solutions and services to develop AI-enhanced systems, including using ML and deep learning capabilities to make IP and tools more automated and produce optimized results faster. AI can be helpful in determining optimal layouts (to increase manufacturing yield or improve performance), or to improve energy efficiency (reducing the distance data needs to travel or the resistance and capacitance of moving that data). For instance, Morgan Stanley estimates that ML algorithms reduce the number of design simulations needed from millions without ML to a few thousand with it.  

Management historically pursued smaller bolt-on acquisitions to round out technology offerings or establish a foothold in a new adjacency. For instance, in 2022 they bought OpenEye, which provides computational molecular modeling and simulation software used by pharma and biotech companies for drug discovery. That same year they bought Future Facilities, which provides electronics cooling analysis and energy performance optimization solutions for data center design and operations using physics-based 3D digital twins. 

Management has carefully created a culture around its engineering competency. Roughly 60% of their total employee base are R&D engineers and another 20% are field engineers. The CFO talks to a culture steeped in “servant leadership,” as the company was originally organized “by engineers, for engineers” to help in the design process as customers chased Moore’s Law. They also manage the business as a “compounder” (their term), with a long-term strategy built around high return investments meant to produce strong compounded returns for shareholders over many years.  

Business Quality

Cadence is an outstanding business that sports many attractive characteristics. 

 

Highly stable revenues.

Management considers roughly 85-90% of revenues to be “recurring,” which includes software arrangements, services, royalties, maintenance on IP licenses and hardware, and operating leases of hardware. The remaining 10-15% relates to sales of emulation and prototyping hardware and individual IP licenses, which can be a bit lumpier, but also tends to largely track software sales.

Their contracts average around three years in duration, so most of the coming year’s revenue is known and in backlog at the beginning of the year. Furthermore, absent companies going bankrupt, the amount of revenue that is at risk each quarter is small (on average, about 1/12 of total annual revenue) given the contractual agreements with customers. As it takes two years to design a chip, and new designs represent the future for customers’ businesses, the risk of attrition is low. Wall has said they have something like 99.9% renewal rates, other than customers that are acquired or go bankrupt. Canceling a contract puts the customer at the end of the cue, effectively implementing a two year pause on tech innovation. A CTO would be committing career suicide by doing that. Therefore, even in a period of macro weakness, revenue streams at Cadence should be stable. Wall also said it’s exceptionally rare for a renewal to be at a lower value than the expiring contract.

In addition, there’s a component of customer stickiness due to switching costs, as it is difficult for customers to change providers for this type of complex software that is imbedded in customer processes. The sales cycle, which is 3 to 6 months, speaks to this stickiness, as do the high levels of customer retention. 

Cadence provides a mission critical service (EDA and SD&A) in a mission critical industry (semiconductors and electronics systems) that represents a great value within the total design project cost for customers. 

Let’s look at EDA and SD&A first. EDA is a necessary and important part of the design process for a chip. Without EDA software, technology companies couldn’t build these complex masterpieces of modern science. Similar comments could be made about SD&A, as it is critical to optimize and verify performance and other attributes of electronic systems. Engineers in customers’ R&D labs work with Cadence’s software tools all day, every day.

Next let’s look at the industry’s importance. It goes without saying that semiconductors and electronic systems play a massive role in today’s modern society, including:

  • Aerospace and defense

  • AI

  • AR

  • Automotive (including ADAS)

  • Communications (including 5G networks)

  • Edge computing

  • Gaming

  • Healthcare (including drug discovery, proteomics, and genome sequencing)

  • Hyperscale computing / data center infrastructure

  • IoT

  • Industrial equipment (including factory automation and 3D printing)

  • Mobile devices (smartphones, watches/wearables, tablets)

  • Networking

  • Omniverse / digital twins

  • PCs

  • Speakers

  • Televisions

  • Transportation

  • VR

It’s not hyperbole to say that the global economy rests on the shoulders of this industry.

Finally, let’s look at the value equation for Cadence’s services. Morgan Stanley estimates that it costs $100 million to $1 billion to design a state-of-the-art processor, with several hundred engineers working for 12-18 months:  

Improving efficiency for this design process can lead to major savings. For example, if an advanced chip costs ~$500 million to design, and Cadence’s tools can eliminate the need for 10% of the research staff for the project, that could lead to $50 million in savings. Furthermore, designing the chip well the first time avoids extremely expensive mistakes down the line. For instance, just producing a photomask costs around $10 million (per Colossus Business Breakdowns), and the cost of producing finished chips that need to be thrown out could dwarf that figure.

Another way to look at it is from a macro level. Cadence has said that about 10% of customers’ R&D goes to EDA, and industry sources show R&D spend by chip companies in the U.S. alone was $59 billion in 2022 (per SIA). The company and other third parties peg the EDA market at around $10 billion globally, which implies global R&D spend on chips is perhaps around $100 billion. In comparison to the $574 billion in total global semiconductor sales in 2022 (per SIA), R&D would therefore work out to around 17%, while EDA itself would be less than 2%. That is a tiny amount for the value it provides, and that doesn’t even account for the trillions of dollars spent on the products that use those chips (the cloud, smartphones, PCs, etc.). 

Demand for EDA and SD&A stems from the combination of increasing complexity in electronics and customer investment in new designs and products. Said differently, demand comes from technological progress and investment in R&D. These tend to be non-cyclical areas of spending, as R&D is one of the last areas that customers will want to cut absent a draconian downturn. Here is some industry data (per SIA for the U.S. only, which can be a proxy for the global market): 

Furthermore, demand is widespread, impacted by almost every industry on the planet, as more and more companies incorporate technological solutions in their businesses and products. In the 2000s, chips mainly went into PCs. In the 2010s, they mainly went into mobile devices. Now, they go into just about everything. As Devgan said, “So almost all semiconductors in the world will require some form of our software to do the design and same thing, increasingly, for electronic systems. So this is all geographies, all verticals.” This widespread demand creates a diversification effect that smooths out the impact of individual industry cycles.

Ultimately, the proof of Cadence’s revenue stability is in the pudding. The following chart shows Cadence’s revenue going back to 2010 (per Macrotrends):